Technology

Alvand follows a rigorous, time-tested design flow.

Ultra Low Power / Small Die ADC/DAC

Alvand's smartCAP™ is the collection of our patented and proprietary Metal-Oxide-Metal (MOM) capacitor structures and design flow that is utilized in our IPs. Different proprietary techniques are used to design high-precision Op-amps and high-speed, small area switches, enabling us to deliver world-class ADCs / DACs. Our highly advanced custom digital correction techniques, MOM caps, pipeline architecture, substrate noise management and internal regulator design techniques allow us to have high-precision and high-speed for our design.

Alvand's robust design and high-yield methodology is based on statDESIGN™ flow. This unique internal flow has been proven over many IPs that are in mass production. This statistical design flow is based on hierarchical behavior modeling and takes into consideration statistical variations and circuit imperfections. A high predictable yield is achieved for our IPs by utilizing statDESIGN™.

Multi-Channel ADC/DAC Architecture

Alvand's high performance, ultra-small and ultra-low power multi-channel ADC/DAC IPs are leaders in wired/wireless communication and image processing markets. Our specialized reference and clock distribution schemes ensure excellent channel-to-channel matching and low cross-talk among channels. Our ADC/DAC channel layouts have a narrow pitch which ensures excellent aspect ratios for our multi-channel ADC/DAC IPs.

On-chip low power and low noise regulator minimizes power supply requirements for our IPs. Our verified in-house integration flow and patented substrate noise isolation techniques allow us to integrate 16/32/64 channel ADCs with large-size DSP core on a single silicon die.

CAD Methodologies

Alvand's CAD environment encompasses proprietary advanced analog automation algorithms and offers significant reductions in design-to-tape-out time by as much as 5X or more. Knowledge of deep sub-micron device physics, fabrication processes, ESD and reliability issues, substrate noise, and signal integrity are incorporated into our CAD methodology in order to efficiently achieve first silicon successes. The in-house tool, smartMigrator™, is used to port both schematics and layouts of Alvand's high-end IPs from and to various technologies, process nodes, and metal options.

In addition to the design automation, EDA views of each IP including Verilog model files, Liberty timing models, LEF, and Phantom views are generated automatically. To guarantee the accuracy of all deliverables of an IP, thorough checks in various levels are carried out in Alvand's Automated Design Verification Environment (ADVE) where a set of utilities perform detailed QA.

EDA Tools

Alvand has developed its own proprietary design and verification flow, which is based on market leading and state of the art EDA tools. Alvand's front-end design flow is based on leading Cadence design tools while the physical verification flow utilizes the leading Mentor Graphics verification tools. Having a good understanding of speed-precision trade off, gained from the many successful First Silicon Tapeouts, we employ BDA's state of the art simulator to achieve highest speed and precision.

Our EDA tool vendors are:

Automated Delivery Platform (ADP)

Alvand has developed an Automated Delivery Platform (ADP) for the delivery of all IPs "Design Kits" to customers. The delivery is fully streamlined and easy for customers to obtain requested Design Kits.

For each IP, Alvand maintains a golden database which is released after rigorous QA and verifications. The ADP collects various deliverables from this golden database and delivers them to the customer in different pre-scheduled phases. The ADP assures an accurate and prompt delivery.

To counter increasing security risks, Alvand maintains several secure FTP servers dedicated to the fast transfer of Design Kits to customers.