Frequently Asked Questions (FAQ)

 

 

A: We provide the following:
- Full datasheet.
- Physical design database (GDSII format).
- LVS netlist (SPICE compatible).
- Footprint (.LEF format).
- Behavioral model (Verilog model).
- Timing model (.LIB format).
- Integration guidelines and support.
- Silicon validation report.
- Evaluation board and test chip (based on request and availability).

A: Yes. You should refer to the Integration Guidelines provided with the IP in the design kit for more details.

A: No. The CDL netlist provided is for LVS purpose only and does not represent all the spice model parameters.

A: You can stream-in the GDSII file to a new cadence (or other tool) library and then the top level of the IP cell can be instantiated into your chip.

A: The IP includes the minimum bypass cap inside. However, based on the power and ground routing and bond wire impedance, we recommend the addition of bypass capacitors. Please refer to the Integration Guidelines provided with the IP in the design kit for more details.

A: Yes. We offer standard support for integration of the IP and it is included in the base IP license agreement.

A: The design kit is in a Golden depository database which has extensive Q&A procedure. Alvand utilizes proprietary "Automated Delivery Platform (ADP)" to deliver the database of the IP design kit. The delivery takes place in different phases, as predefined in ADP through secure and dedicated FTP servers. This procedure provides the customer with high level of confidence and accuracy during transfer.

A: Alvand will provide ADC model based on transistor and Verilog A which models the input circuitry of the ADC as part of the datasheet of the IP.

A: Alvand will provide the phantom, LEF and verilog EDA views ahead of GDSII delivery for integration purposes.