White Paper
Mixed Signal IP for Precision Distance Measurement
1.Introduction
Traditionally, distance measurement has always been related to the RF domain. Today many complicated SoCs have been designed to include mixed-signal base-band and digital domain functionalities for high precision distance measurement. Due to a very compact silicon area, standard CMOS fabrication procedure and significantly reduced on-board component (BOM) cost, this SoC has a huge potential and value. One of the biggest challenges in this SoC is the front end receive path Analog-to-Digital Converter (ADC). The system requirements are very stringent due to high bandwidth requirement and high sampling speed.
Devices based on this application are targeted at customers in construction, civil and other similar industries. Construction of complicated structures like bridges, skyscrapers require accuracy in the range of millimeters to make the construction reliable.
This article discusses the front end design requirements and system level requirements for this application.
2.Description
The proposed system utilizes the FFT of sine-waves to measure distances very accurately. FFT produces extremely high precision phase measurement and the phase delay can be measured with an accuracy ranging in the order of a few pico-seconds.
A sine-wave at high frequency is sent towards the object from the sensor. After reflection, the time of travel is estimated using the phase difference between the emitted wave and the reflected wave. Fig. 2.1 shows a brief block diagram of the system.
(a)
(b)
Fig. 2.1. SoC block description. (a) System level view. (b) Receiver section.
2.1.Receive SignalA sine wave is sent from the system towards the target at a frequency of 320 MHz. It impinges on the target and gets reflected back. The reflected wave is sent to an ADC and is sub-sampled at a rate of 160MHz.
(a)
(b)
Fig. 2.2. Sine wave sampling. (a) Input wave sampling. (b) ADC block.
A multi-phase PLL is used to reconstruct the receive signal. It generated various phases of the clock and the signal is sampled with these different clocks.
Fig. 2.3. Multi-phase clock from multi-phase PLL.
The phase difference between the clock phases is determined by the multi-phase PLL. Assuming the phase difference to be
Sampling the input signal with multiple phases of the clock, we generate a set of do[n] corresponding to each sampling clock. These points when stringed together represent the input signal and the input signal is regenerated in this fashion using the sub-sampling technique.
Fig. 2.4. Regenerated sine-wave from the various DC points.
We can calculate the distance by utilizing the phase information of the transmitted and received waves, frequency of the wave and the speed of wave.
Where v is velocity of wave, Tfl is total time of travel and d is distance. Phase difference and travel time are given by,
ΔΦ= ωΔt
where is phase of received wave, ref is phase of reference wave, is angular velocity and fo is frequency of received signal.
Assuming the speed of light to be 0.3 mm/ps, for an accuracy of 1 mm the time should be accurate within 3 ps. This implies the phase difference obtained from the FFT must be accurate to
ΔΦ = 3p * 2 * 320M = 6m rad
3.Accuracy of Phase Estimation
Accuracy in phase estimation is the most critical part of the procedure. The SNR of the whole system has a vital role in deciding this critical error component and better SNR leads to higher accuracy of the estimation. To improve SNR the following techniques are utilized:
This is a very common technique to improve the SNR of the ADC. Taking the average over multiple samples allows you to reduce the random thermal noise component [1].
Where ydc is output of LPF (averaging), ydc is standard deviation of ydc, n is standard deviation of do[n], Ns is number of samples and Gav is noise reduction from averaging.
Assuming number of samples per clock phase to be 16 (Ns = 16), due to power and time constraints. The noise reduction obtained due to averaging is:
Gav = 12 dB
3.2.Number of FFT PointsAdditional noise reduction can be achieved by increasing the number of points for FFT calculation [2]. The number of FFT points is directly controlled by the number of clock phases generated by the multiphase PLL.
Fig. 3.1. FFT of regenerated wave (harmonics omitted)
The FFT consists of the signal, DC offset and the harmonics. The phase estimation is affected by the noise at Bin2 to a large extent.
where, nsys is RMS noise at specific bin, ydc is RMS noise floor, N is No. of FFT points.
Assuming the number of FFT points to be 16, improvement due to this technique is
= 9dB
Noise amplitude at bin # 2 (m=2, N=16, fs=160MHz), a critical source of error, is a random variable with Rayleigh distribution.
(a) (b)
Fig. 3.2. (a) Phase error due to random noise. (b) Rayleigh PDF of noise.
SNR of the complete system (SNRsys) can be calculated as follows.
With a 3σ assumption it can be calculated that the worst
case noise power is 9dB. For an accuracy of 1mm, e
is 6m rad, i.e.,
emax
for the system is found to be:
A major factor in the above equation is SNRSYS which is again governed by the SNR of the ADC. To maximize the estimation accuracy, we need to maximize the SNR of the ADC.
The linearity of ADC causes the shape of the reconstructed signal to deviate from a pure sine wave. Due to limited number of phase (FFT points) the higher order harmonics will fold back and happen in the same bin of the signal. In case of N=16 and fs=160MHz, the H7 (seventh harmonic) will get folded back and fall on the signal bin. Due to this reason, the SNRsys of the system must be better than the seventh harmonic to reduce the phase estimation error.
4.ADC Architecture
The choice of ADC architecture is very limited for this application. Due to its high sampling clock frequency and high input bandwidth, there are not many architectures that are suitable for this application.
4.1.Pipeline ArchitecturePipeline is one architecture that suits this application. The SNR and sampling frequency (160 MHz / 320 MHz) requirements can be achieved by implementing a 10-bit pipeline ADC. The performance of the pipeline ADC will comfortably cover the requirement of the system with sufficient margin.
All the IPs provided by Alvand Technologies, are highly optimized for low power and silicon area. The pipeline ADC consists of cascaded stages each containing high power consuming Op-Amps. Even this low power may be considered high in certain places where the power needs to be reduced further. For most applications, this architecture is good match for the SoC.
4.2.Interleaved SAR ArchitectureAn alternate architecture that is a good fit for this application is interleaved SAR.
Interleaving two parallel SAR ADCs is ideal for this application. Errors arising due to parallelism like, offset, gain mismatch and phase mismatch create tones at either DC or fs/2. Since FFT bin # 2 is the most critical, phase estimation is not affected due to these errors.
Interleaved SAR architecture at this high-speed is very challenging and a slight mismatch in timing causes harmonics. The phase estimation error is good as long as the amplitude of the harmonics are not high.
Alvand Technologies specializes in high performance design and parallelism at high speeds. This architecture is a very good for applications requiring extremely low power design.
5.Summary
Several important aspects are to be examined carefully before selecting a mixed-signal IP for the distance measurement application SoC. The ADC requirements are stringent and the design is complex. It requires vast experience and design knowledge to successfully develop this IP. At these high speeds, integration of the IP into the SoC is a challenge of its own. It requires a dedicated and well seasoned team of engineers from the IP house to support the customer during the integration phase.
References
[1]: Athanasios Papoulis, “Probability, Random Variables and Stochastic Processes”, Third Edition. McGraw Hill International Edition, 1991.
[2]: John G. Proakis, Dimitris G. Manolakis, “Digital Signal Processing”, Third Edition, Prentice Hall, 1996.
